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INTEGRATED CIRCUITS
DATA SHEET
TDA8768 12-bit high-speed Analog-to-Digital Converter (ADC)
Preliminary specification Supersedes data of 1998 Feb 25 File under Integrated Circuits, IC02 1998 Aug 26
Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
FEATURES * 12-bit resolution * Sampling rate up to 55 MHz * -3 dB bandwidth of 190 MHz * 5 V power supplies * Binary or twos-complement CMOS outputs * In-range CMOS-compatible output * TLL-CMOS compatible static digital inputs * 3 to 5 V CMOS-compatible digital outputs * Differential clock input; Positive Emitter Coupled Logic (PECL)-compatible * Power dissipation 325 mW (typical) * Low analog input capacitance (typical 2 pF), no buffer amplifier required * Integrated sample-and-hold amplifier * Differential analog input * External amplitude range control * Voltage controlled regulator included. QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO INL DNL fCLK(max) PARAMETER analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current integral non-linearity differential non-linearity maximum clock frequency TDA8768H/4 TDA8768H/5 Ptot total power dissipation 40 55 - - - 325 fCLK = 4 MHz; fi = 400 kHz fCLK = 4 MHz; fi = 400 kHz fCLK = 4 MHz; fi = 400 kHz CONDITIONS MIN. 4.75 4.75 3.0 - - - - - TYP. 5.0 5.0 3.3 33 30 3.2 2.0 0.6 GENERAL DESCRIPTION APPLICATIONS
TDA8768
* High-speed analog-to-digital conversion for - Video signal digitizing - High Definition TV (HDTV) - Imaging (camera scanner) - Medical imaging - Telecommunication - Base-station receiver.
The TDA8768 is a bipolar 12-bit Analog-to-Digital Converter (ADC) optimized for telecommunications and professional imaging. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 55 MHz. All static digital inputs (SH, CE and OTC) are TTL and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used.
MAX. 5.25 5.25 5.25 tbf tbf tbf 4.5 1.0 - - tbf
UNIT V V V mA mA mA LSB LSB MHz MHz mW
ORDERING INFORMATION TYPE NUMBER TDA8768H/4 TDA8768H/5 PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2 SAMPLING FREQUENCY (MHz) 40 55
1998 Aug 26
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
BLOCK DIAGRAM
TDA8768
handbook, full pagewidth
VCCA1 VCCA2 VCCA3 VCCA4 2 9 3 41
CLK 35
CLK 36
VCCD1 VCCD2 37 15
OTC 18
CE 19 21 D11
n.c.
1, 5 to 8, 12 to 14, 16 CLOCK DRIVER
MSB 22 D10 23 D9 24 D8 25 D7
TDA8768
Vref 11
AMP CMOS OUTPUTS VI VI 43 42 sampleand-hold SH 39 ANALOG-TO-DIGITAL CONVERTER LATCHES
26 D6 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0 33 LSB VCCO data outputs
OVERFLOW/ UNDERFLOW LATCH
CMOS OUTPUT
20
IR
44
10
4
40
38
17
34
MGR470
AGND1
AGND2
AGND3
AGND4
DGND1
DGND2
OGND
Fig.1 Block diagram.
1998 Aug 26
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
PINNING SYMBOL n.c. VCCA1 VCCA3 AGND3 n.c. n.c. n.c. n.c. VCCA2 AGND2 Vref n.c. n.c. n.c. VCCD2 n.c. DGND2 OTC CE IR D11 D10 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 DESCRIPTION not connected analog supply voltage 1 (+5 V) analog supply voltage 3 (+5 V) analog ground 3 not connected not connected not connected not connected analog supply voltage 2 (+5 V) analog ground 2 reference voltage input not connected not connected not connected digital supply voltage 2 (+5 V) not connected digital ground 2 control input twos complement output; active HIGH chip enable input (CMOS level; active LOW) in-range output data output; bit 11 (MSB) data output; bit 10 CLK VCCD1 DGND1 SH AGND4 VCCA4 VI VI AGND1 36 37 38 39 40 41 42 43 44 SYMBOL D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCCO OGND CLK PIN 23 24 25 26 27 28 29 30 31 32 33 34 35
TDA8768
DESCRIPTION data output; bit 9 data output; bit 8 data output; bit 7 data output; bit 6 data output; bit 5 data output; bit 4 data output; bit 3 data output; bit 2 data output; bit 1 data output; bit 0 (LSB) output supply voltage (3 to 5.25 V) output ground complementary clock input; active LOW clock input digital supply voltage 1 (+5 V) digital ground 1 sample-and-hold enable input (CMOS level; active HIGH) analog ground 4 analog supply voltage 4 (+5 V) positive analog input voltage negative analog input voltage analog ground 1
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
TDA8768
38 DGND1
44 AGND1
40 AGND4
34 OGND
handbook, full pagewidth
37 VCCD1
41 VCCA4
36 CLK
35 CLK
39 SH
43 VI
42 VI
n.c. VCCA1 VCCA3 AGND3 n.c. n.c. n.c. n.c. VCCA2
1 2 3 4 5 6 7 8 9
33 VCCO 32 D0 31 D1 30 D2 29 D3
TDA8768H
28 D4 27 D5 26 D6 25 D7 24 D8 23 D9
AGND2 10 Vref 11 n.c. 12 n.c. 13 n.c. 14 VCCD2 15 n.c. 16 DGND2 17 OTC 18 CE 19 IR 20 D11 21 D10 22
MGR469
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output supply voltage supply voltage difference VCCA - VCCD VCCD - VCCO VCCA - VCCO VI Vi(p-p) input voltage at pins 42 and 43 input voltage at pins 35 and 36 for differential clock drive (peak-to-peak value) output current storage temperature operating ambient temperature junction temperature referenced to AGND -1.0 -1.0 -1.0 0.3 - +1.0 +4.0 +4.0 note 1 note 1 note 1 CONDITIONS MIN. -0.3 -0.3 -0.3
TDA8768
MAX. +7.0 +7.0 +7.0 V V V V V V V V
UNIT
VCCA VCCD
IO Tstg Tamb Tj Note
- -55 -10 -
10 +150 +85 150
mA C C C
1. The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 V and +7.0 V provided that the supply voltage differences VCC are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITION in free air VALUE 75 UNIT K/W
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
TDA8768
CHARACTERISTICS VCCA = V2 to V44, V9 to V10, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V; VCCO = V33 to V34 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to 70 C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 C, VI(p-p) - VI(p-p) = 2.0 V and CL = 10 pF; unless otherwise specified. SYMBOL Supply VCCA VCCD VCCO ICCA ICCD ICCO Inputs CLK AND CLK (REFERENCED TO DGND) VIL VIH IIL IIH Zi Ci VCLK(p-p) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance differential AC input voltage (peak-to-peak value) for switching (VCLK - VCLK) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current VIL = 0.8 V VIH = 2.0 V VCCD = 5 V; note 1 VCCD = 5 V; note 1 VCLK or VCLK = 3.19 V VCLK or VCLK = 3.83 V fCLK = 40 MHz fCLK = 40 MHz DC voltage level = 2.5 V 3.19 3.83 -10 - 2 - 0.5 - - - - - - - 3.52 4.12 - 10 - 2 2.0 V V A A k pF V analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current fCLK = 4 MHz; fi = 400 kHz 4.75 4.75 3.0 - - - fCLK = 40 MHz; fi = 4.43 MHz - 5.0 5.0 3.3 33 30 3.2 11 5.25 5.25 5.25 45 37 tbf tbf V V V mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
OTC, SH AND CE (REFERENCED TO DGND); see Tables 1 and 2 VIL VIH IIL IIH IIL IIH Ri Ci VI(CM) 0 2.0 -20 - - - fi = 4.43 MHz fi = 4.43 MHz VI = VI; output code 2047 VCCA = 5 V VCCA = 4.75 V VCCA = 5.25 V tbf tbf tbf 3.6 3.35 3.85 tbf tbf tbf V V V 100 - - - - - 10 10 - - 0.8 VCCD - +20 - - - 2 V V A A A A k pF
VI AND VI (REFERENCED TO AGND); VREF = VCCA - 1.825 V; see Table 1 LOW-level input current HIGH-level input current input resistance input capacitance common mode input voltage
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8768
MAX.
UNIT
Voltage controlled regulator input Vref (referenced to AGND); note 2 Vref(FS) Iref full-scale fixed voltage input current Vref = VCCA - 1.825 V VCCA = 5 V - - - 3.175 0.5 2.0 - 10 - V A V
VI(p-p) - VI(p-p) input voltage amplitude (peak-to-peak value) Outputs (referenced to OGND)
DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND) VOL VOH Io LOW-level output voltage HIGH-level output voltage output current in 3-state IOL = 2 mA IOH = -0.4 mA output level between 0.5 V and VCCO 0 VCCO - 0.5 -20 - - - 0.5 VCCO +20 V V A
Switching characteristics CLOCK FREQUENCY fCLK; see Fig.3 fCLK(min) fCLK(max) minimum clock frequency maximum clock frequency TDA8768H/4 TDA8768H/5 tCLKH tCLKL clock pulse width HIGH clock pulse width LOW 40 55 8.5 8.5 - - - - - - - - MHz MHz ns ns SH = HIGH - - 2 MHz
Analog signal processing; 50% clock duty factor; VI - VI = 2.0 V; Vref = VCCA - 1.825 V; see Table 1 LINEARITY INL DNL Eoffset integral non-linearity differential non-linearity offset error fCLK = 4 MHz; fi = 400 kHz fCLK = 4 MHz; fi = 400 kHz; no missing code VCCA = VCCD = VCCO = 5 V; Tamb = 25 C; VI = VI; output code = 2047 VCCA = VCCD = VCCO = 5 V; Tamb = 25 C; VI(p-p) - VI(p-p) = 2.0 V -3 dB; full scale input fi = 4.43 MHz fi = 4.43 MHz - - fi = 4.43 MHz; note 4 - -75 -70 -66 - - - dB dB dB - - tbf 2.0 0.6 -11 4.5 1.0 tbf LSB LSB mV
EG(FS)
gain error amplitude (full scale); spread from device to device
-5
-
+5
%
BANDWIDTH (fCLK = 55 MHz); note 3 B analog bandwidth tbf - 190 - - 0 MHz HARMONICS (fCLK = 40 MHz) hfund(FS) htot(FS) fundamental harmonics (full scale) harmonics (full scale); all components second harmonic third harmonic THD total harmonic distortion dB
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
SYMBOL THERMAL NOISE Nth(rms) thermal noise (RMS value) grounded input; fCLK = 40 MHz fi = 4.43 MHz fi = 10 MHz fi = 20 MHz SIGNAL-TO-NOISE RATIO; note 5 S/N signal-to-noise ratio without harmonics; - fCLK = 40 MHz; fi = 4.43 MHz - - - - - - - tbf tbf 67 - - 0.25 PARAMETER CONDITIONS MIN. TYP.
TDA8768
MAX.
UNIT
tbf
LSB
SPURIOUS FREE DYNAMIC RANGE DRsf spurious free dynamic range tbf tbf tbf 69 tbf tbf - - - dB dB dB
dB
EFFECTIVE NUMBER OF BITS; note 5 Nbit effective number of bits fi = 4.43 MHz TDA8768H/4 (fCLK = 40 MHz) fi = 10 MHz fi = 15 MHz effective number of bits fi = 4.43 MHz TDA8768H/5 (fCLK = 55 MHz) fi = 10 MHz fi = 15 MHz fi = 20 MHz INTERMODULATION; note 6 TTIR d3 two-tone intermodulation rejection third order intermodulation distortion fCLK = 40 MHz fCLK = 40 MHz 66 67 - - dB dB 10.3 tbf tbf 9.9 tbf tbf tbf - - - - - - - bits bits bits bits bits bits bits
BIT ERROR RATE BER bit error rate fCLK = 40 MHz; fi = 4.43 MHz; VI = 16 LSB at code 2047 - 10-15 tbf times/ sample
Timing (CL = 10 pF); see Fig.3 and note 7 td(s) th td sampling delay time output hold time output delay time VCCO = 5.25 V VCCO = 3.0 V 3-state output delay times; see Fig.4 tdZH tdZL tdHZ tdLZ enable HIGH enable LOW disable HIGH disable LOW - - - - 14 16 16 14 18 20 20 18 ns ns ns ns - 4 - - - 10 13 2 - 15 18 ns ns ns ns
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
Notes 1. The circuit has two clock inputs: CLK and CLK. There are four modes of operation:
TDA8768
a) PECL mode 1: (DC level varies 1 : 1 with VCCD) CLK and CLK inputs are at differential PECL levels. b) PECL mode 2: (DC level varies 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level varies 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.5 V (peak-to-peak value) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor. 2. It is possible with an external reference connected to pin Vref to adjust the ADC input range. This voltage has to be referenced to VCCA. For VCCA - 1.825 V, the differential input voltage amplitude is 2 V (peak-to-peak value). 3. The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. 4. THD (total harmonic distortion) is obtained with the addition of the first five harmonics: F THD = 20 log --------------------------------------------------------------------------------------------------------------2 2 2 2 2 (2nd) + (3rd) + (4th) + (5th) + (6th) where F is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input. 5. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SNR: SNR = Nbit x 6.02 + 1.76 dB. 6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (-6 dB below full-scale for each input signal). d3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. 7. Output data acquisition: the output data is available after the maximum delay of td.
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
Table 1
TDA8768
Output coding with differential inputs (typical values to AGND); VI(p-p) - VI(p-p) = 2.0 V; Vref = VCCA - 1.825 V BINARY OUTPUTS TWOS COMPLEMENT OUTPUTS D11 TO D0 100000000000 1 0 0 0 0 0 0 0 0 0 00 100000000001 111111111111 011111111110 011111111111 011111111111
CODE Underflow 0 1 2047 4094 4095 Overflow
VI(p-p) <3.1 3.1 - - 3.6 - - 4.1 >4.1
VI(p-p) >4.1 4.1 - - 3.6 - - 3.1 <3.1
IR D11 TO D0 0 1 1 1 1 1 0 000000000000 000000000000 000000000001 011111111111 111111111110 111111111111 111111111111
Table 2 Mode selection OTC 0 1 X(1) Note 1. X = don't care. Table 3 Sample-and-hold selection SH 1 0 active inactive; tracking mode SAMPLE-AND-HOLD CE 0 0 1 binary; active twos complement; active high impedance D0 TO D11 AND IR
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
TDA8768
handbook, full pagewidth
tCLKL tCLKH HIGH CLK 50 % LOW sample N sample N + 1 sample N + 2
VI
tds DATA D0 to D11 DATA N-2 DATA N-1 td
th HIGH DATA N DATA N+1
MGR472
50 % LOW
Fig.3 Timing diagram.
handbook, full pagewidth
V CCD CE 0V tdHZ HIGH 90 % output data tdLZ HIGH output data LOW 10 % TEST V CCD 3.3 k TDA8768 15 pF CE S1 t dLZ t dZL t dHZ t dZH S1 VCCD VCCD DGND DGND
MBG856
50 %
tdZH
50 % tdZL LOW
50 %
fCE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
APPLICATION INFORMATION
TDA8768
handbook, full pagewidth
5V 100 nF
SH mode
5V 100 nF
220 nF input 100
1:1 100
VI CLK CLK VI VCCA R1
(2) (1)
5V n.c. 1 2 44 43 42 41 40 39 38 37 36 35 34 100 nF 33 32 31 30 29 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9
5V 100 nF n.c. n.c. n.c. 100 nF 5V 100 nF Vref
(3)
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 n.c. n.c. 5V 100 nF n.c. n.c. IR
4.7 F
10 nF
R2
TDA8768
28 27 26 25 24 23
n.c.
D10 D11 (MSB) chip select input output format select
MGR471
The analog, digital and output supplies should be separated and decoupled. (1) Single-ended clock signals can be applied if required. (2) R1 and R2 must be determined in order to obtain a middle voltage of 3.6 V; see common mode input voltage. In addition, to ensure a sufficient analog input stability, the minimum current into these resistors must be approximately 1 mA. (3) Vref must be decoupled to VCCA.
Fig.5 Application diagram.
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
TDA8768
handbook, full pagewidth
R2 220 100 nF
270 TTL input
(1)
R1 500 CLK Z0 = 50 PECL Z0 = 50 CLK R1 500 100 nF 36 35
D TRANSLATOR
270
TDA8768
R2 220
MGL474
If the clock lines are more than 1 inch long they must be matched. In fact, the 27 resistor will be changed by the series connection of R1 and R2, with R1 = Zo placed close to pins CLK and CLK. (1) 50 matched line (Zo, L).
Fig.6 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator.
100 nF
handbook, full pagewidth
VCCD R1 82 TTL input
(1)
R1 82 CLK 35
D TRANSLATOR PECL CLK R2 120 R2 120 36
TDA8768
MGL473
The value of R1 and R2 must be chosen in order to meet the following relations: V CCD x R2 R1 x R2 3 V = ---------------------------- and Z0 = --------------------R1 + R2 R1 + R2 (1) 50 matched line (Zo, L).
Fig.7
Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator and Thevenin parallel terminations.
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
TDA8768
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
TDA8768
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8768
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
NOTES
TDA8768
1998 Aug 26
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital Converter (ADC)
NOTES
TDA8768
1998 Aug 26
19
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/750/02/pp20
Date of release: 1998 Aug 26
Document order number:
9397 750 03378

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